1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of fabricating an embedded DRAM (dynamic random-access memory) device which is a type of DRAM device that has a memory cell array and associated logic transistor array integrated on the same chip.
2. Description of Related Art
An embedded DRAM device is a type of DRAM device in which the memory cell array and the associated logic circuit array are integrated on the same chip. This design scheme allows the DRAM device to have very fast access speed, making the DRAM device useful in data processing systems that require high speed, such as image processing systems, where large amounts of data are processed. Fundamentally, an embedded DRAM device includes an array of logic circuit elements and an array of transfer FETs (field effect transistor), each of which is coupled to a capacitive element for charge storage. Each transfer FET serves as a switching element between the associated capacitive element and the bit line. Whether the data stored in the DRAM cell is 1 or 0 depends on whether or not electric charge is transferred via the transfer FET to the capacitive element where it is stored.
FIGS. 1A-1E are schematic sectional diagrams used to depict the steps involved in a conventional method of fabricating an embedded DRAM device. In FIGS. 1A-1E, only one DRAM cell is shown, and the right part of the wafer indicated by the reference numeral 170 shows the area where the transfer FET of the DRAM cell is formed, while the left part indicated by the reference numeral 172 shows the area where a logic circuit element in association with the DRAM cell is formed. In this embodiment, the logic circuit element is also an FET. Both the transfer FET 170 and the logic circuit element 172 are formed on the same substrate, which is a P-type silicon substrate 100, for example. A plurality of field oxide layers 102 are formed in the substrate 100 to serve as isolation areas isolating all the transfer FET 170 and the logic circuit element 172 from each other. These field oxide layers 102 can be formed either through a LOCOS (local oxidation of silicon) process or by first performing an STI (shallow trench isolation) process to form trenches in the substrate 100 and then performing a CVD (chemical-vapor deposition) process to deposit oxide into the trenches.
In order to increase the conductivity of the gates of the FETs, conventional methodology forms a polysilicon layer and a metal silicide layer over the polysilicon layer to make a so-called polycide layer. The polycide layer is then selectively removed to form the desired gates. Another conventional method is to first deposit a polysilicon layer, then remove selected portions of the polysilicon layer, and then perform a self-aligning silicide process so as to form metal silicide layers respectively over the polysilicon layers and the source/drain regions. One drawback to the self-aligning silicide process, however, is that it can cause a further thinning of the shallow junction between the source/drain regions and the substrate, thus resulting in leakage current in the capacitive elements of the DRAM device that are coupled to the source/drain regions. Therefore, the self-aligning silicide process is not used to form metal silicide layers over the source/drain regions 124 in order to prevent leakage current. Furthermore, in order to increase the conductivity of the source/drain regions of those FETs in the logic circuit, a conventional method is to perform a self-aligning silicide process to form metal silicide layers over the source/drain regions 126.
Each transfer FET 170 includes a pair of source/drain regions 124 between which a channel is defined, a gate oxide layer 108 formed over the channel, a polysilicon layer 112 formed over the gate oxide layer 108, a layer of metal silicide 116 formed over the polysilicon layer 112, and a gate topping layer 120 formed over the metal silicide layer 116. The gate oxide layer 108, the polysilicon layer 112, the metal silicide layer 116, and the gate topping layer 120 in combination constitute a gate structure, as collectively indicated by the reference numeral 104. In a similar manner, each logic circuit element 172 includes a pair of source/drain regions 126 between which a channel is defined, a gate oxide layer 110 formed over the channel, a polysilicon layer 114 formed over the gate oxide layer 110, a layer of metal silicide 118 formed over the polysilicon layer 114, and a gate topping layer 122 formed over the metal silicide layer 118. The gate oxide layer 110, the polysilicon layer 114, the metal silicide layer 118, and the gate topping layer 122 in combination constitute a gate structure, as collectively indicated by the reference numeral 106.
Referring next to FIG. 1B, an annealing process is performed on the wafer of FIG. 1A at a temperature of 900-1,000.degree. C. This annealing process activates the doped impurities in the source/drain regions 124, 126 and thus more evenly distributes the impurities in the source/drain regions 124, 126 (hereinafter, the annealed source/drain regions are instead designated respectively by the reference numeral 124a, 126a in order to distinguish one from the other). Next, sidewall spacers 128, 130 are respectively formed on the sidewalls of the gate structures 104, 106. Subsequently, an insulating layer 140 is formed over the area 170 where the transfer FET is formed
Referring further to FIG. 1C, in the subsequent step, a metal layer, such as a titanium layer 142, is formed through a PVD (physical vapor deposition) process over the entire top surface of the wafer.
FIG. 1D shows the subsequent step, in which an annealing process is performed on the entire wafer at a temperature of 700-800.degree. C. In this annealing process, part of the titanium layer 142 over the source/drain regions 126a is converted into silicide. Subsequently, a wet etching process is performed on the wafer by submerging the entire wafer in an aqueous solution of H.sub.2 O.sub.2 and NH.sub.4 OH, in which the unreacted part of the titanium in the titanium layer 142 is removed. The remaining portions of the titanium silicide layer are here designated by the reference numeral 150. After this, another annealing process is performed on the wafer, whereby the titanium silicide layer 150 over the source/drain regions 126a can be reduced in electrical resistance. The foregoing process for forming this titanium silicide layer 150 is customarily referred to as a self-aligning silicide process.
FIG. 1E shows the subsequent step, in which a thick dielectric layer 152 is formed over the entire top surface of the wafer. The dielectric layer 152 then is selectively removed to form a contact window 154 to expose one of the source/drain regions 124a of the transfer FET. Subsequently, a conventional process is performed to form a capacitive element including a first conductive layer 156, a dielectric layer 158, and a second conductive layer 160. The first conductive layer 156 comes into electrical contact with the exposed one of the source/drain regions 124a via the contact window 154. This completes the fabrication of the embedded DRAM device.
One drawback to the foregoing method, however, is that in the self-aligning silicide process for forming the titanium silicide layer 150, a certain amount of the silicon in the substrate 100 is depleted due to reaction with the titanium, which leads to a further thinning of the shallow P-N junction between the source/drain regions 126a and the substrate 100. A leakage current thus can occur at this thin shallow P-N junction. This thinning effect is particularly serious when the embedded DRAM device is further downsized for higher integration.
With high integration, a new type of CMOS (complementary metal-oxide semiconductor), called dual-gate CMOS structure, is used to replace old types of CMOS structures. A dual-gate CMOS structure refers to a semiconductor structure that includes both N-type and P-type MOS transistors on the same chip, where the NMOS transistor has an N-type highly doped polysilicon gate and the PMOS transistor has a P-type highly doped polysilicon gate. The dual-gate CMOS structure can be used in an embedded DRAM device to provide enhanced performance. A conventional method for fabricating an embedded DRAM device with dual-gate CMOS structure is depicted in the following with reference to FIG. 2.
FIG. 2 is a schematic perspective diagram used to depict the initial steps involved in a conventional method for fabricating an embedded DRAM device with dual-gate CMOS structure.
As shown, a substrate 200 is prepared, in which a P-well 201a, a N-well 201b, and an isolation area 202 are formed. Next, a gate structure 204 is formed, which includes a gate oxide layer 208, two juxtaposed polysilicon layers 212a, 212b over the gate oxide layer 208, a metal silicide layer 216 over the two polysilicon layers 212a, 212b, and a gate topping layer 220 over the metal silicide layer 216. By the dual-gate CMOS technology, the first polysilicon layer 212a is located above the P-well 201a and the isolation area 202 and is highly doped with an N-type impurity element, while the second polysilicon layer 212b is located above the N-well 201b and the isolation area 202 and is highly doped with a P-type impurity element. After the gate structure 204 is formed, a photolithographic and ion-implantation process is performed to define and form a first pair of source/drain regions 224 in association with the first polysilicon layer 212a (the N-type highly doped polysilicon layer) and a second pair of source/drain regions 225 in association with the second polysilicon layer 212b (the P-type highly doped polysilicon layer). Next, an annealing process is performed on the wafer at a temperature of 900-1,000.degree. C. to activate the doped impurities in these source/drain regions 224, 225. The first polysilicon layer 212a and the source/drain regions 224 in combination constitute an NMOS transistor, while the second polysilicon layer 212b and the source/drain regions 225 in combination constitute a PMOS transistor.
The subsequent steps taken to complete the fabrication of this embedded DRAM device with dual-gate CMOS structure are the same as those depicted in reference to FIGS. 1B-1E, so detailed description of them is not be repeated.
One drawback to the foregoing method for fabricating an embedded DRAM device with dual-gate CMOS structure, however, is that the annealing process to activate the doped impurities in the source/drain regions 224, 225 also causes the N-type impurities in the first polysilicon layer 212a and the P-type impurities in the second polysilicon layer 212b to be subjected to an undesired inter-diffusion effect through the metal silicide layer 216. As a bad consequence of this, the first and second polysilicon layers 212a, 212b can suffer from a reduced impurity concentration, thus resulting in a drift in the threshold voltage of the resultant DRAM device.